clock gating meaning in Chinese
时钟选通
Examples
- Clock gating is an efficient way of reducing dynamic power consumption in digital circuits
时钟闸控是降低数位电路动态功率消耗的有效方法。 - To avoid the idleness state and the corresponding power dissipation in sequential circuits , a clock gating technique and a multi - code assignment using redundant state is adanced to reduce power dissipation
为抑制时序电路中的冗余现象，研究了时序电路的门控时钟技术，并利用t型触发器进行时序电路设计。 - In this paper , low power flip - flops designs by the reduction of the load of clock or the data path ; by the reduction of clock swing ; by the reduction of clock frequency and by the reduction of those idle transitions in cmos circuits with clock gating are discussed
与此相对应的，在本论文中，分别对将少时钟负载或数据通路的负载的触发器设计；减小时钟信号幅度的触发器设计；降低时钟频率的双边沿触发器设计以及应用门控技术来减少触发器无效跳变设计的触发器结构进行了讨论。 - According to elaborate analysis of clock logic in general purpose processor , we apply multi - bit clock gated flip - flops design to reduce the power of registers and clock trees concurrently , so the power of the clock network in processors can be drastically reduced . 3 . a low power issue queue architecture is proposed
一方面利用带门控使能的触发器电路降低时钟节点的平均翻转,另一方面通过多比特触发器的采用进一步降低了时钟树规模,从而在不增加asic物理设计复杂度的情况下大大降低了龙芯处理器的时钟网络功耗; 3 .提出了乱序多发射队列的低功耗结构。